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Tenstorrent

Santa Clara

Processor Design

Total Raised

$1B

Valuation

$3.2B

Segment

Semiconductors

Open Roles

114

Open Roles (114)

AI/ML Physical Design Flow Engineer

Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Advanced Physical Design

Mid

AI Performance Simulation Architect

United States · Performance Model

Mid

ASIC Networking Engineer

United States · Architecture

Mid

Automotive and Robotics SOC Architect

United States · Automotive Architecture

Mid

Business Development Lead, India

Bengaluru, Karnataka, India · Experience

Lead

Chiplet Physical Design Engineer

United States · Architecture

Mid

C++ Machine Learning Engineer, AI Models Training

Santa Clara, California, United States · AI Software

Mid

C++ Machine Learning Engineer, Models Training

Gdańsk, Pomeranian Voivodeship, Poland; Warszawa, Masovian Voivodeship, Poland · AI Software

Mid

CPU Architect, Load-Store

United States · Performance Model

Mid

CPU Design Verification Technical Lead

United States · Design Verification

Lead

Developer Relations Engineer, Advocacy

Austin, Texas, United States; Fort Collins, Colorado, United States; Portland, Oregon, United States; Santa Clara, California, United States; United States · Dev Rel

Mid

Developer Relations Engineer, Tools

Austin, Texas, United States; Fort Collins, Colorado, United States; Portland, Oregon, United States; Santa Clara, California, United States; Toronto, Ontario, Canada; United States · Dev Rel

Mid

DFT Engineer, Automotive Robotics

Munich, Germany · Automotive

Mid

Director of Customer Engineering

Toronto, Ontario, Canada · AI Hardware

Manager

Director of Quality, Supply Chain

Toronto, Ontario, Canada · Supply Chain

Manager

Director, RISC-V Software Ecosystem

United States · RISC V

Manager

Director, Systems & Solutions

Austin, Texas, United States; North America; Santa Clara, California, United States; Toronto, Ontario, Canada · Systems Engineering

Manager

Emulation Engineer, Automotive Robotics

Munich, Germany · Automotive

Mid

Engineering Program Manager, RISCV

Austin, Texas, United States · RISC V

Manager

Engineer, PCIe Validation

Vancouver, British Columbia, Canada · Si Val / Qual

Mid

Experienced Technical Recruiter

Belgrade, Serbia · Recruiting

Mid

Fabric SOC Architect

United States · Architecture

Mid

Field Application Engineer - AI Systems & Solutions

Munich, Germany · Systems Engineering

Mid

Field Application Engineer, Automotive Robotics

Munich, Germany · Automotive

Mid

Field Applications Engineer, IP Product

Austin, Texas, United States; Fort Collins, Colorado, United States; Raleigh, North Carolina, United States; Santa Clara, California, United States; Toronto, Ontario, Canada; Vancouver, British Columbia, Canada · IP Product Eng

Mid

Formal Verification Engineer

United States · Design Verification

Mid

Functional Safety Hardware Engineer, Automotive Robotics

Munich, Germany · Automotive

Mid

GCC Compiler Engineer

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Runtime

Mid

Head of ISV Partnerships, Experience GTM

United States · Experience

Manager

High Speed AI Interconnect Signal Integrity Engineer

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Systems Engineering

Mid

Infrastructure and Platform Development Engineer

Austin, Texas, United States; Gdańsk, Pomeranian Voivodeship, Poland; Santa Clara, California, United States; Toronto, Ontario, Canada; Warszawa, Masovian Voivodeship, Poland · AI Software

Mid

Infrastructure and Platform Engineer, Metal

United States · AI Software

Mid

Infrastructure Automation Engineer, Metal

Toronto, Ontario, Canada · AI Software

Mid

Lead Hardware Solutions Architect

Toronto, Ontario, Canada · AI Hardware

Lead

Machine Learning Engineer, AI Models

Cyprus · ML Models

Mid

Memory Architect

North America · Architecture

Mid

Mixed-Signal IC Layout Design Engineer

United States · Mixed Signal Design

Mid

Mixed Signal IC Layout Design Engineer - Contractor

North America · Mixed Signal Design

Mid

Munich Site Manager

Munich, Germany · Automotive

Manager

Package Design Engineer

Toronto, Ontario, Canada; 新北市, New Taipei City, Taiwan · Packaging

Mid

PCB Layout Engineer

Santa Clara, California, United States; Toronto, Ontario, Canada · Systems Engineering

Mid

Performance Architect, AI HW

Toronto, Ontario, Canada · Tensix

Mid

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

United States · Mixed Signal Design

Mid

Physical Design Engineer - STA

Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Advanced Physical Design

Mid

Power Architect

Toronto, Ontario, Canada · Tensix

Mid

Power Architect, AI Data Center Chiplets

United States · Architecture

Mid

Power Design Engineer

Tokyo, Japan · Architecture

Mid

Project Manager, People Team

Santa Clara, California, United States · Human Resources

Manager

Regional Sales Lead, Singapore

Asia · Experience

Lead

RISC-V AI / HPC & Agentic Software Engineer

新北市, New Taipei City, Taiwan · Architecture

Mid

RISC-V AI / HPC & Agentic Software Engineering Lead

North America · Architecture

Lead

Risc-V Architect

Toronto, Ontario, Canada · Tensix

Mid

RISC-V CPU Microarchitecture / RTL

United States · CPU

Mid

Senior Design Verification Engineer, AI HW

Toronto, Ontario, Canada · Tensix

Senior

Senior DFT Engineer, Architecture

Tokyo, Japan · Architecture

Senior

Senior Engineer, System-Level Design Verification

Toronto, Ontario, Canada · AI Hardware

Senior

Senior Physical Design Engineer

Tokyo, Japan · Architecture

Senior

Senior Tax Manager

United States · Finance

Senior

Signal Integrity Engineer

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Systems Engineering

Mid

Silicon Power & Characterization Engineer

Toronto, Ontario, Canada · Si Val / Qual

Mid

Silicon Power & Characterization Lead

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Si Val / Qual

Lead

Silicon Validation Engineer

Santa Clara, California, United States · Mixed Signal Design

Mid

Site Reliability Engineer, Metal

Toronto, Ontario, Canada · AI Software

Mid

SOC Architect

Munich, Germany · Automotive

Mid

SOC Emulation Engineer - Hardware Emulation Infrastructure

Austin, Texas, United States; Santa Clara, California, United States · SoC

Mid

SoC Physical Design Verification Engineer

Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Physical Design

Mid

SoC Top-Level Physical Design Engineer

Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Physical Design

Mid

Software Architect, Automotive Robotics

Munich, Germany · Automotive

Mid

Software Engineer

Tokyo, Japan · ML Models

Mid

Software Engineer, AI Compiler

Austin, Texas, United States · AI Compiler

Mid

Software Engineer, Kernel Development and Optimization

Gdańsk, Pomeranian Voivodeship, Poland; Warszawa, Masovian Voivodeship, Poland · OPs

Mid

Software Engineer, Metal Runtime (API & Abstractions)

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Runtime

Mid

Software Engineer, Metal Runtime (Core Systems)

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Runtime

Mid

Software Engineer, TT-Distributed

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Scale Out

Mid

Software Engineer, TT-Fabric

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Scale Out

Mid

Sr. Engineer, Kernel Development and Optimization

Belgrade, Serbia · OPs

Senior

Sr. Engineer, Performance Infrastructure

Austin, Texas, United States · RISC V

Senior

Sr Engineer, Server Inference

Belgrade, Serbia · Product Software Engineering

Senior

Sr. Engineer, SoC Design Verification

Boston, Massachusetts, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · SoC

Senior

Sr. Engineer, Software - AI Compiler

Belgrade, Serbia · AI Compiler

Senior

Sr. Engineer, Software - AI Compiler

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · AI Compiler

Senior

Sr. IP Product Engineer, AI Processor

Toronto, Ontario, Canada; Vancouver, British Columbia, Canada · IP Product Eng

Senior

Sr. Software Engineer, AI Compiler

Toronto, Ontario, Canada · AI Compiler

Senior

Sr. Software Engineer, Observability and Telemetry

Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Scale Out

Senior

Sr.Staff, Design Verification - CPU Cluster / SoC

Bengaluru, Karnataka, India · RISC V

Staff

Sr. Staff Design Verification Engineer, Automotive Robotics

Munich, Germany · Automotive

Staff

Sr Staff Engineer, ASIC Design Methodology

Boston, Massachusetts, United States; Toronto, Ontario, Canada · SoC

Staff

Sr Staff Engineer, CPU System Microarchitect

Bengaluru, Karnataka, India · RISC V

Staff

Sr Staff Engineer, CPU System Microarchitect

Austin, Texas, United States · RISC V

Staff

Sr. Staff Engineer, Post-Silicon Validation

Bengaluru, Karnataka, India · RISC V

Staff

Sr Staff Engineer, SoC RTL Design

Toronto, Ontario, Canada · Digital Design

Staff

Sr. Staff, HR Business Partner

Austin, Texas, United States; Boston, Massachusetts, United States; Santa Clara, California, United States · Human Resources

Staff

Sr. Staff RTL Engineer, Automotive Robotics

Munich, Germany · Automotive

Staff

Staff Business Applications Engineer, IT

United States · IT

Staff

Staff Design for Test Engineer

Austin, Texas, United States; Santa Clara, California, United States · Silicon

Staff

Staff, Design for Test Engineer (DFT)

Bengaluru, Karnataka, India · Silicon

Staff

Staff Design for Test STA Engineer

Austin, Texas, United States; Santa Clara, California, United States · DFT and Test

Staff

Staff Engineer, CPU Core Verification

Austin, Texas, United States · RISC V

Staff

Staff Engineer Design Verification

Bengaluru, Karnataka, India · RISC V

Staff

Staff Engineer, Emulation Technical Lead

Austin, Texas, United States · RISC V

Staff

Staff Engineer, Physical Design

Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Advanced Physical Design

Staff

Staff Engineer, SoC RTL Engineer

Tokyo, Japan · Architecture

Staff

Staff Engineer, Software Release and Packaging - RISC V

Australia; Canada; United States · RISC V

Staff

Staff, Ethernet Validation Engineer

Santa Clara, California, United States; Vancouver, British Columbia, Canada · Si Val / Qual

Staff

Staff Field Application Engineer, Customer Success

Santa Clara, California, United States · Experience

Staff

Staff Mixed Signal Design Engineer, Silicon Validation

Santa Clara, California, United States; Toronto, Ontario, Canada · IP Product

Staff

Staff Physical Design Engineer – EMIR

Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Physical Design

Staff

Staff Software Engineer, Cloud Infrastructure

United States · Cloud Platform

Staff

Staff Technical Program Manager, AI Systems and IP Delivery

North America · AI Hardware

Staff

Static Timing Analysis (STA) Methodology Engineer

Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Advanced Physical Design

Mid

Sustaining Test Engineer

新北市, New Taipei City, Taiwan · DFT and Test

Mid

System IP & Site Lead India

Bengaluru, Karnataka, India · RISC V

Lead

Technical Program Manager, Architecture

Santa Clara, California, United States · Architecture TPM

Manager

Verification Engineer

Japan · Architecture

Mid