Tenstorrent
Santa Clara
Total Raised
$1B
Valuation
$3.2B
Segment
Semiconductors
Open Roles
114
Open Roles (114)
AI/ML Physical Design Flow Engineer
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Advanced Physical Design
AI Performance Simulation Architect
United States · Performance Model
ASIC Networking Engineer
United States · Architecture
Automotive and Robotics SOC Architect
United States · Automotive Architecture
Business Development Lead, India
Bengaluru, Karnataka, India · Experience
Chiplet Physical Design Engineer
United States · Architecture
C++ Machine Learning Engineer, AI Models Training
Santa Clara, California, United States · AI Software
C++ Machine Learning Engineer, Models Training
Gdańsk, Pomeranian Voivodeship, Poland; Warszawa, Masovian Voivodeship, Poland · AI Software
CPU Architect, Load-Store
United States · Performance Model
CPU Design Verification Technical Lead
United States · Design Verification
Developer Relations Engineer, Advocacy
Austin, Texas, United States; Fort Collins, Colorado, United States; Portland, Oregon, United States; Santa Clara, California, United States; United States · Dev Rel
Developer Relations Engineer, Tools
Austin, Texas, United States; Fort Collins, Colorado, United States; Portland, Oregon, United States; Santa Clara, California, United States; Toronto, Ontario, Canada; United States · Dev Rel
DFT Engineer, Automotive Robotics
Munich, Germany · Automotive
Director of Customer Engineering
Toronto, Ontario, Canada · AI Hardware
Director of Quality, Supply Chain
Toronto, Ontario, Canada · Supply Chain
Director, RISC-V Software Ecosystem
United States · RISC V
Director, Systems & Solutions
Austin, Texas, United States; North America; Santa Clara, California, United States; Toronto, Ontario, Canada · Systems Engineering
Emulation Engineer, Automotive Robotics
Munich, Germany · Automotive
Engineering Program Manager, RISCV
Austin, Texas, United States · RISC V
Engineer, PCIe Validation
Vancouver, British Columbia, Canada · Si Val / Qual
Experienced Technical Recruiter
Belgrade, Serbia · Recruiting
Fabric SOC Architect
United States · Architecture
Field Application Engineer - AI Systems & Solutions
Munich, Germany · Systems Engineering
Field Application Engineer, Automotive Robotics
Munich, Germany · Automotive
Field Applications Engineer, IP Product
Austin, Texas, United States; Fort Collins, Colorado, United States; Raleigh, North Carolina, United States; Santa Clara, California, United States; Toronto, Ontario, Canada; Vancouver, British Columbia, Canada · IP Product Eng
Formal Verification Engineer
United States · Design Verification
Functional Safety Hardware Engineer, Automotive Robotics
Munich, Germany · Automotive
GCC Compiler Engineer
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Runtime
Head of ISV Partnerships, Experience GTM
United States · Experience
High Speed AI Interconnect Signal Integrity Engineer
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Systems Engineering
Infrastructure and Platform Development Engineer
Austin, Texas, United States; Gdańsk, Pomeranian Voivodeship, Poland; Santa Clara, California, United States; Toronto, Ontario, Canada; Warszawa, Masovian Voivodeship, Poland · AI Software
Infrastructure and Platform Engineer, Metal
United States · AI Software
Infrastructure Automation Engineer, Metal
Toronto, Ontario, Canada · AI Software
Lead Hardware Solutions Architect
Toronto, Ontario, Canada · AI Hardware
Machine Learning Engineer, AI Models
Cyprus · ML Models
Memory Architect
North America · Architecture
Mixed-Signal IC Layout Design Engineer
United States · Mixed Signal Design
Mixed Signal IC Layout Design Engineer - Contractor
North America · Mixed Signal Design
Munich Site Manager
Munich, Germany · Automotive
Package Design Engineer
Toronto, Ontario, Canada; 新北市, New Taipei City, Taiwan · Packaging
PCB Layout Engineer
Santa Clara, California, United States; Toronto, Ontario, Canada · Systems Engineering
Performance Architect, AI HW
Toronto, Ontario, Canada · Tensix
Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
United States · Mixed Signal Design
Physical Design Engineer - STA
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Advanced Physical Design
Power Architect
Toronto, Ontario, Canada · Tensix
Power Architect, AI Data Center Chiplets
United States · Architecture
Power Design Engineer
Tokyo, Japan · Architecture
Project Manager, People Team
Santa Clara, California, United States · Human Resources
Regional Sales Lead, Singapore
Asia · Experience
RISC-V AI / HPC & Agentic Software Engineer
新北市, New Taipei City, Taiwan · Architecture
RISC-V AI / HPC & Agentic Software Engineering Lead
North America · Architecture
Risc-V Architect
Toronto, Ontario, Canada · Tensix
RISC-V CPU Microarchitecture / RTL
United States · CPU
Senior Design Verification Engineer, AI HW
Toronto, Ontario, Canada · Tensix
Senior DFT Engineer, Architecture
Tokyo, Japan · Architecture
Senior Engineer, System-Level Design Verification
Toronto, Ontario, Canada · AI Hardware
Senior Physical Design Engineer
Tokyo, Japan · Architecture
Senior Tax Manager
United States · Finance
Signal Integrity Engineer
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Systems Engineering
Silicon Power & Characterization Engineer
Toronto, Ontario, Canada · Si Val / Qual
Silicon Power & Characterization Lead
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Si Val / Qual
Silicon Validation Engineer
Santa Clara, California, United States · Mixed Signal Design
Site Reliability Engineer, Metal
Toronto, Ontario, Canada · AI Software
SOC Architect
Munich, Germany · Automotive
SOC Emulation Engineer - Hardware Emulation Infrastructure
Austin, Texas, United States; Santa Clara, California, United States · SoC
SoC Physical Design Verification Engineer
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Physical Design
SoC Top-Level Physical Design Engineer
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Physical Design
Software Architect, Automotive Robotics
Munich, Germany · Automotive
Software Engineer
Tokyo, Japan · ML Models
Software Engineer, AI Compiler
Austin, Texas, United States · AI Compiler
Software Engineer, Kernel Development and Optimization
Gdańsk, Pomeranian Voivodeship, Poland; Warszawa, Masovian Voivodeship, Poland · OPs
Software Engineer, Metal Runtime (API & Abstractions)
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Runtime
Software Engineer, Metal Runtime (Core Systems)
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Runtime
Software Engineer, TT-Distributed
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Scale Out
Software Engineer, TT-Fabric
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Scale Out
Sr. Engineer, Kernel Development and Optimization
Belgrade, Serbia · OPs
Sr. Engineer, Performance Infrastructure
Austin, Texas, United States · RISC V
Sr Engineer, Server Inference
Belgrade, Serbia · Product Software Engineering
Sr. Engineer, SoC Design Verification
Boston, Massachusetts, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · SoC
Sr. Engineer, Software - AI Compiler
Belgrade, Serbia · AI Compiler
Sr. Engineer, Software - AI Compiler
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · AI Compiler
Sr. IP Product Engineer, AI Processor
Toronto, Ontario, Canada; Vancouver, British Columbia, Canada · IP Product Eng
Sr. Software Engineer, AI Compiler
Toronto, Ontario, Canada · AI Compiler
Sr. Software Engineer, Observability and Telemetry
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · Scale Out
Sr.Staff, Design Verification - CPU Cluster / SoC
Bengaluru, Karnataka, India · RISC V
Sr. Staff Design Verification Engineer, Automotive Robotics
Munich, Germany · Automotive
Sr Staff Engineer, ASIC Design Methodology
Boston, Massachusetts, United States; Toronto, Ontario, Canada · SoC
Sr Staff Engineer, CPU System Microarchitect
Bengaluru, Karnataka, India · RISC V
Sr Staff Engineer, CPU System Microarchitect
Austin, Texas, United States · RISC V
Sr. Staff Engineer, Post-Silicon Validation
Bengaluru, Karnataka, India · RISC V
Sr Staff Engineer, SoC RTL Design
Toronto, Ontario, Canada · Digital Design
Sr. Staff, HR Business Partner
Austin, Texas, United States; Boston, Massachusetts, United States; Santa Clara, California, United States · Human Resources
Sr. Staff RTL Engineer, Automotive Robotics
Munich, Germany · Automotive
Staff Business Applications Engineer, IT
United States · IT
Staff Design for Test Engineer
Austin, Texas, United States; Santa Clara, California, United States · Silicon
Staff, Design for Test Engineer (DFT)
Bengaluru, Karnataka, India · Silicon
Staff Design for Test STA Engineer
Austin, Texas, United States; Santa Clara, California, United States · DFT and Test
Staff Engineer, CPU Core Verification
Austin, Texas, United States · RISC V
Staff Engineer Design Verification
Bengaluru, Karnataka, India · RISC V
Staff Engineer, Emulation Technical Lead
Austin, Texas, United States · RISC V
Staff Engineer, Physical Design
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Advanced Physical Design
Staff Engineer, SoC RTL Engineer
Tokyo, Japan · Architecture
Staff Engineer, Software Release and Packaging - RISC V
Australia; Canada; United States · RISC V
Staff, Ethernet Validation Engineer
Santa Clara, California, United States; Vancouver, British Columbia, Canada · Si Val / Qual
Staff Field Application Engineer, Customer Success
Santa Clara, California, United States · Experience
Staff Mixed Signal Design Engineer, Silicon Validation
Santa Clara, California, United States; Toronto, Ontario, Canada · IP Product
Staff Physical Design Engineer – EMIR
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Physical Design
Staff Software Engineer, Cloud Infrastructure
United States · Cloud Platform
Staff Technical Program Manager, AI Systems and IP Delivery
North America · AI Hardware
Static Timing Analysis (STA) Methodology Engineer
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Advanced Physical Design
Sustaining Test Engineer
新北市, New Taipei City, Taiwan · DFT and Test
System IP & Site Lead India
Bengaluru, Karnataka, India · RISC V
Technical Program Manager, Architecture
Santa Clara, California, United States · Architecture TPM
Verification Engineer
Japan · Architecture